TMS 9900 Breadboard or PCB System
EPROM Binary Images
Programming - TIBUG and EVMBUG System Monitors
Programming - BASIC
Programming - Forth
This TMS 9900 system project provides a similar, minimal system to my TMS 9995 breadboard project, but using the Texas Instruments
first-generation TMS 9900 16-bit microprocessor. The system can be built either on a breadboard, or on a PCB (contact me if you
want a PCB - I'll order them in small batches once a couple of people have
expressed an interest).
The microcomputer is designed to interface with a Terminal program running on a PC, and run a system monitor, BASIC interpreter and Forth interpreter from EPROM - note though that there is no facility to load or save programs on this simple system. Pre-programmed EPROMs are available for purchase for users who do not have the facilities to program their own.
The breadboard system is easy to modify, expand and experiment with as the user wishes. On the PCB, take-off points are included for all the main signals to enable the system to be expanded off the board. The PCB also includes a small prototyping area.
This web page provides the specification, circuit diagram and technical description of the system.
The project requires the parts listed in the table below. Some (UK) sources for purchasing them and approximate costs are included.
|Circuit Diagram Reference||Description||Source||Approx. Cost
|-||(If building on the breadboard) 3 pieces of solderless breadboard, each section approx. 175 × 65 mm (64 contact points (holes) long by 10 wide, 2 pairs of bus strips along each edge of the board, see this photo)||eBay||£10 for the 3 sections|
|U1||TMS 9900 microprocessor||eBay||£10|
|U2||TIM 9904A clock generator||eBay||£10|
|U3||TMS 9901 programmable systems interface||eBay||5|
|U4||ICL7660SCPAZ voltage converter||eBay||£2|
|U5||74LS32 quad 2 input OR gate IC||eBay||£1|
|U6||74LS04 hex inverter IC||eBay||£1|
|U7, U8||32K byte 27256 or 27C256 EPROM, 120ns or faster (ST part # M27C256B-12XF1 works)||eBay||£2 each|
|U9, U10||32K byte 62256 static RAM, 120ns or faster, 0.6" wide package (Hitachi part # HM62256BLP-7 works)||eBay||£5 each|
|U11||74LS138 3-to-8 line decoder IC||eBay||£1|
|U12||TMS 9902A asynchronous communications controller||eBay||£10|
|U13||MAX232CPE (or MAX232EPE) dual RS-232 transceiver||eBay||£2|
|U14||Dallas DS1210 non-volatile memory controller||eBay||£10|
|X1||12 MHz crystal, HC-49U package (AEL
Crystals part # X12M000000L188 works)
(Take care trying to use a crystal in a low profile HC-49/S package - I tried one of these and found the clock was unreliable, especially if you touch the capacitor and inductor forming the tank circuit.)
|C1||47uF tantalum capacitor, 16V||Maplin ‑ part # WW76H||£0.60|
|C2||50pF ceramic capacitor||eBay||£0.50|
|C3, C5 - C10, C14 - C20, C26||0.1μF ceramic decoupling capacitor||Maplin ‑ part # BX03D||£1.30 for the 14|
|C4||22uF electrolytic capacitor, 25V||Maplin ‑ part # WW64U||£0.20|
|C11||22μF electrolytic capacitor, 35V||Maplin ‑ part # KQ65V||£0.30|
|C12, C13||10uF electrolytic capacitor, 16V||Maplin ‑ part # AT98G||£0.60 for the 2|
|C21 - C25||1μF electrolytic capacitor, 63V||Maplin ‑ part # AU09K||£1.75 for the 5|
|L1||3.3uH inductor (choke), axial||eBay||£1|
|R1 - R4||16 Ohm metal film 0.6W resistor||Maplin ‑ part # M16R||£0.40 for the 4|
|R5||100K metal film 0.6W resistor||Maplin ‑ part # M100K||£0.10|
|R6||100 Ohm metal film 0.6W resistor||Maplin ‑ part # M100R||£0.10|
|R7||4.7K metal film 0.6W resistor||Maplin ‑ part # M4K7||£0.10|
|R8||220 Ohm metal film 0.6W resistor||Maplin ‑ part # M220R||£0.10|
|R9 - R11||10K metal film 0.6W resistor||Maplin ‑ part # M10K||£0.30 for the 3|
|RN1 - RN3||Resistor network, 10K, 9 pin (8 commoned resistors)||eBay||£1.00 for the 3|
|D1||LED, 3mm, red||Maplin ‑ part # UK18U||£0.20|
|SW1||Single pole, push-to-make, PCB mount, non locking switch||Maplin ‑ part # KR91Y||£1.50|
|(connects to J2)||+5V to +12V step up converter module (see eBay item number 332049746567; check pinout against PCB if using a different module)||eBay||£2|
|B1||CR2032 3V battery and PCB mount holder||eBay||£1|
|J1||DC power socket (female), 5.5 × 2.1mm, PCB mount||eBay||£1|
|J2 - J5, J7||0.1" pin strip, cut to size as required, with suitable jumpers||Maplin ‑ part # JW59P, N24AN||£2 + £2.50|
|J6||9-way D-type socket (female), PCB mount||eBay||£2|
|-||IC sockets if building on the PCB (all 0.1"
• 1 × 64 pin, 0.9" wide
• 1 × 40 pin
• 4 × 28 pin, 0.6" wide
• 1 × 20 pin
• 1 × 18 pin
• 2 × 16 pin
• 2 × 14 pin
• 2 × 8 pin
A circuit diagram for the project is available here, and a high resolution photograph of the breadboard system here. The following description should be read in conjunction with the component datasheets, links to which are given in the References section below.
TIM 9904A clock generator U2 generates the four-phase clock required by the TMS 9900 processor U1. The frequency of the internal oscillator is established by 12 MHz crystal X1. The LC circuit formed by inductor L1 and capacitor C2 connected across the tank inputs of U2 is tuned to the crystal fundamental frequency. Series resistors R1 - R4 minimise overshoot and undershoot on the 12V clock lines. The Æ3 clock, at TTL signal levels, is also used as a timing clock for the TMS 9901 Programmable Systems Interface (PSI) U3 and the TMS 9902 Asynchronous Communications Controller (ACC) U12.
Resistor R5 and capacitor C1 provide a 'power on reset' input to the D-type flip-flop within U2. The flip-flop output, FFQ, is fed to the active-low reset inputs of the processor U1 and PSI U3. Switch SW1 and resistor R6 provide a manual reset function.
The following processor inputs are pulled high by resistors R9 - R11:
EPROMs U7, U8 and static RAMs U9, U10 are connected directly to the processor address and data buses. Note that at the time Texas Instruments labelled their address and data bus lines the opposite way round to the rest of the industry, so the low numbered processor address and data bus lines are connected to the high numbered EPROM and RAM address and data bus lines, and the high numbered processor lines are connected to the low numbered EPROM and RAM lines. The EPROM and RAM /OE (Output Enable) inputs are connected to the processor DBIN output, which is inverted by U6b to form /DBIN. When /DBIN is active low, the processor has disabled its data bus output buffers to allow external memory to output data onto the data bus. The EPROM /CE (Chip Enable) input is derived by ORing address bus line A0 with the processor /MEMEN (Memory Enable) output, such that the EPROM is enabled during memory cycles in the address range >0000 - >7FFF. The RAM /CE input is derived in a similar way by inverting address bus line A0 and ORing it with /MEMEN such that RAM is enabled during memory cycles in the address range >8000 - >FFFF.
The RAM most-significant (MS) address bit A14 is connected to the PSI U3 pin P1. After a reset, all the programmable pins on U3 are programmed as inputs, and P0 to P6 are pulled low by resistor network RN1, so by default the lower 32K bank of RAM is used. By writing a logic 1 to pin P1 through the Communications Register Unit (CRU) interface, the upper 32K bank of RAM can be selected (although care must be taken to synchronise the switch as the program's workspace registers will change to whatever values are in the corresponding memory addresses in the upper bank of RAM).
The EPROM MS address bit A14 is connected to a 3-way jumper which enables the following configurations:
The pair of RAMs have been fitted to the breadboard in a piggyback fashion to reduce the wiring involved in connecting them, while the EPROMs have been fitted in ZIF sockets to make them easy to replace.
3-to-8 line decoder U11 decodes address bus lines A7, A8 and A9 during CRU input/output cycles when /MEMEN is high to provide chip enable signals for 8 blocks of 32 bits of CRU address space. Output /Y0 is active low when addressing CRU bits 0 - 31, /Y1 is active when addressing bits 32 - 63, and so on.
TMS 9902 ACC U12 is a CRU peripheral device which provides the interface between the processor and a serial, asynchronous, RS‑232 communications channel. The connection to address decoder U11 maps the device to processor CRU address bits 0 - 31 (equating to a CRU base address of >0000). RS‑232 driver/receiver U13 generates ±10V supplies from the single +5V supply and provides signal level conversion between RS‑232 signal levels (±3V to ±25V) and the TTL signal levels used by U12. A simple 3-wire RS‑232 interface is implemented through connector J6.
TMS 9901 PSI U3 is another CRU peripheral device which provides interrupt control, I/O ports, and an interval timer/clock. The system interface consists of 22 pins divided into 3 groups. The 6 pins in Group 1 (/INT1 - /INT6) are normally dedicated to interrupt inputs, but may also be used as input ports. Group 2 (/INT7_P15 - /INT15_P7) consists of 9 pins which can be individually programmed as interrupt inputs, input ports or output ports. The remaining 7 pins which comprise Group 3 (P0 - P6) are dedicated as individually programmable I/O ports. After a reset, all the programmable pins are programmed as inputs. The pins in Groups 1 and 2 are pulled high by resistor networks RN2 and RN3, and are made available on connector J4. The pins in Group 3 are pulled low by resistor network RN1, and are made available on connector J3. Two pins in Group 3 are used for one of the RAM and EPROM address bits, as described above. When one or more pins are programmed as interrupt inputs, the interrupt section of the TMS 9901 prioritises and encodes the highest priority active interrupt and outputs this code to the processor on the IC0 - IC3 lines along with an active /INTREQ signal. The connection to address decoder U11 maps the TMS 9901 to a CRU base address of >0040.
The circuit requires a single +5V regulated supply, which is input through connector J1. Capacitor C11 provides power supply smoothing. LED D1 provide a 'power on' indication, with resistor R8 limiting the current through the LED. Most of the components operate from this single +5V power supply, with the exception of the processor U1 which also requires -5V and +12V supplies, and the clock generator U2 which also requires a +12V supply. The -5V supply is generated from the +5V supply by voltage converter U4. For the +12V supply, a +5V to +12V step up converter module is used which is soldered to connector J2. The supply to individual ICs is decoupled by capacitors C3 - C10, C14 - C20 and C26.
The two RAM ICs are powered through the non-volatile memory controller U14 which provides battery backup and write-protects the RAMs when the Vcc supply is out of tolerance.
TIM 9904A four-phase clock generator and driver data manual
TMS 9900 microprocessor data manual
TMS 9901 programmable systems interface data manual
TMS 9902ANL asynchronous communications controller data sheet
Dallas DS1210 non-volatile memory controller data sheet
ST M27256 EPROM data sheet
Hitachi HM62256LP-10 static RAM data sheet
74LS04 hex inverter IC data sheet
74LS32 quad 2 input OR gate IC data sheet
74LS138 3-to-8 line decoder IC data sheet
MAX232CPE dual RS-232 transceiver data sheet
System monitor. The project uses a modified version of the TIBUG system monitor from TI's TM 990 range of microcomputer modules and the EVMBUG system monitor from TI's TMS 9995 Evaluation Module. TIBUG and EVMBUG are described on this page.
The BASIC interpreter is based on a port of the Powertran Cortex Power BASIC made for my TM 990 computer. The Cortex BASIC user guide is available here.
The Forth interpreter is based on fig-FORTH 9900 Release 1.0 (March 1981). Details on fig-FORTH are available at www.forth.org.
A combined EPROM binary image is provided which contains the EVMBUG system monitor and Cortex BASIC in the lower 32K bank and the TIBUG system monitor in the upper 32K bank. Select the lower 32K bank by setting jumper J5 to the 'LO' position and select the upper 32K bank by setting jumper J5 to the 'HI' position.
The link below is to a zip file which contains two EPROM images - one image for the even (most significant) byte, and one for the odd (least significant) byte. Which EPROM goes in which socket is clearly marked on the PCB.
Link to TIBUG, EVMBUG system monitor and Cortex BASIC EPROM image
The TIBUG and EVMBUG system monitors provide an interactive interface between the user and the system. They are described on this page.
If you are new to programming a single board computer of this type, the user manual for the TM 990/100M microcomputer provides a good introduction to the processor architecture and concepts.
The BASIC interpreter is based on a port of the Powertran Cortex Power BASIC made for my TM 990 computer. BASIC is programmed in the EPROM along with a slightly modified version of the EVMBUG monitor. When the system is reset, a menu is displayed: press 1 to run the EVMBUG monitor, or press 2 to run BASIC.
TMS 9900 PCB SYSTEM
BY STUART CONNER
PRESS 1 FOR EVMBUG MONITOR
PRESS 2 FOR CORTEX BASIC
-- TMS 9900 Breadboard BASIC Rev. 1.1 --
[Ported from Cortex BASIC (C)1982 by Stuart Conner]
Cortex BASIC is designed to run from RAM, so to avoid having to rewrite and restructure sections of the code for this breadboard project, the BASIC code is copied from EPROM to RAM and then run from RAM when it is selected at the menu. This leaves 3K of memory free for program storage - but this should be sufficient for 'tinkering' considering that there is no means of saving a program.
The Cortex BASIC user guide is available here.
Mapping between the keys on the Cortex computer and the keys on the PC keyboard is as shown in the following table.
|Cortex Key||PC Keyboard Key|
The version of EVMBUG supplied with BASIC is modified such that the automatic delay functionality after printing each line on a mechanical teletype is disabled. This won't make any difference unless you happen to be using a mechanical teletype ...
When BASIC is in use, all input is automatically converted to upper case.
There are some changes and restrictions in the TMS 9900 implementation as compared to the implementation described in the Cortex user guide:
The Forth interpreter is based on the fig-FORTH 9900 Release 1.0 (March 1981). The source code is available here (the TMS 9900 implementation is slightly modified in terms of the memory pointers used and the input/output routines). Forth is programmed in the EPROM along with a slightly modified version of the EVMBUG monitor. When the system is reset, a menu is displayed: press 1 to run the EVMBUG monitor, or press 2 to run Forth.
TMS 9900 PCB SYSTEM
BY STUART CONNER
PRESS 1 FOR EVMBUG MONITOR
PRESS 2 FOR FIG-FORTH
9900 fig-FORTH Rel 1.0
The Forth code is copied from EPROM to RAM and then run from RAM when it is selected at the menu. All input and output is over the RS-232 interface, and there is no means of loading or saving a program.
Various Forth tutorials are available here. Note that different versions of Forth support slightly different dictionaries so you might find some examples in the tutorials that will not work on the TMS 9900 implementation.
The version of EVMBUG supplied with Forth is modified such that the automatic delay functionality after printing each line on a mechanical teletype is disabled. This won't make any difference unless you happen to be using a mechanical teletype ...